Once formation of semiconductor devices and interconnects on a semiconductor wafer (substrate) is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting on a circuit board. A package is a supporting element for the semiconductor chip that provides mechanical protection and electrical connection to an upper level assembly system such as the circuit board. Two types of packaging technologies are commonly available. The first type is wire bonding that employs bonding pads and solder bumps on the semiconductor chip and on a wirebond package. Bonding wires connect pairs of bonding pads across the semiconductor chip and the wirebond package to provide electrical connection between them. The second type is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pads on the semiconductor chip and another C4 pad on a packaging substrate. Both types of packaging technologies provide a packaged semiconductor chip which may be assembled on the circuit board.
Typically, a semiconductor chip having a large number of input/output (I/O) pins employ C4 packaging since C4 packaging can handle higher density of pins than wire bonding packages. FIG. 1 shows a prior art packaging substrate comprising a core 50 at the center, multiple vertically stacked front metal interconnect layers 20′ located above the core 50, multiple front insulator layers 30 interspersed between the front metal interconnect layers 20′ and above the core 50, multiple vertically stacked back metal interconnect layers 80′, and multiple back insulator layers 70 interspersed between the back metal interconnect layers 80′. Each of the front insulator layers 30 provides electrical isolation between a pair of neighboring front metal interconnect layers 20′. Likewise, each of the back insulator layers 70 provides electrical isolation between a pair of neighboring back metal interconnect layers 80′. Typically, the number of front metal interconnect layers 20′ matches the number of the back metal interconnect layers 80′.
The packaging substrate facilitates formation of electrical link between the semiconductor chip and a system board of a computer. A semiconductor chip is mounted on a die foot print area 12 located on a top surface of the packaging substrate. The die foot print area 12 contains C4 pads on which a semiconductor chip (not shown) may be attached by C4 bonding. The area of the top surface of the packaging substrate outside of the die foot print area 12 is referred to as a packaging substrate top surface 10.
A typical semiconductor chip employing a packaging substrate may comprise about 5,000 input/output nodes. Each of these nodes are electrically connected to a C4 pad on a top surface of the semiconductor chip in a two dimensional array. Typical two dimensional array configurations for the C4 pads include 4 on 8 configuration, which employs C4 solder balls having a diameter of 4 mils (˜100 microns) and a pitch of 8 mils (˜200 microns) in a rectangular array, and 3 on 6 configuration, which employs C4 solder balls having a diameter of 3 mils (˜75 microns) and a pitch of 6 mils (˜150 microns) in a rectangular array. Thus, more than 5,000 C4 solder balls may be formed on the semiconductor chip, which may be typically about 2 cm×2 cm in size.
The front metal interconnect layers 20′ and the back metal interconnect layers 80′ provide electrical connections from the C4 pads on the die foot print area 12 to the bottom of the packaging substrate which contains ball grid array (BGA) pads having a larger dimension than the C4 pads. Typically, BGA pads are in a rectangular array having a pitch on the order of about 1 mm. BGA solder balls having a diameter of about 400 microns are used to attach the packaging substrate to the system board. Typically, Sn—Ag—Cu alloys, which are free of lead, is employed to meet emerging standards for reducing hazardous materials. An alternative method to BGA connection is to employ land grid array (LGA) in which a thin pad containing metal points in a grid are placed between the system board and the substrate. Use LGA facilitates easy removal of a substrate containing expensive electronics for repair purposes.
The packaging substrate also protects the semiconductor chip that is mounted on the die foot print area 12 and modularizes the product development of the semiconductor chip, while simplifying the subsequent integration steps involved in the manufacturing of a larger computer or a consumer electronic product. Ceramic materials or organic materials may be employed for building up a substrate. Ceramic substrates are built layer by layer without the need of a core where as an organic substrates requires a core on which the front and back layers can be built. While ceramic materials offer excellent mechanical strength and a low level of warp relative to organic materials, there is an inherent limitation in wiring density posed by ceramic substrate. It necessarily requires larger number of buildup layers (by a factor of 5 to 10) than that required by a an organic substrate. In contrast, an organic substrate facilitates high density wiring in the front metal interconnect layers 20′ and the back metal interconnect layers 80′, i.e., a packaging substrate employing an organic material for the core 50, the top insulator layers 30, and the bottom insulator layers 80. Typically, approximately 16 levels of the front metal interconnect layers 20′ and the back metal interconnect layers 80′ may accommodate the contents of the electrical wiring in 100 levels in a ceramic package.
The present trend in substrate technology is to transition from ceramic packaging substrates to organic packaging substrates. An organic packaging substrate, i.e., an organic polymer based electronic packaging substrate is a cost effective means to fan out the input/output pads and power supply pads from a semiconductor chip having a large number of pads or pads arranged in a high density. Presence of core 50 in an organic package degrades the electrical parameters of the interconnects as signals have to travel through larger inductive and resistive links called plated through holes. In order to enhance the electrical performance the industry has interest in reducing the core thickness to near 100 um thick if not completely becoming a coreless substrate. Furthermore to reduce the thermal expansion sensitivity, materials for the core 50 having a lower coefficient of thermal expansion (CTE) are being pursued by the packaging industry. Even though the quest for low-CTE materials revolves around organic resins with filled particles, use of silicon or ceramic as the core material can not be overlooked.
The core 50 of an organic packaging substrate is made of fiber reinforced organic or resin material having a thickness from about 400 microns to about 800 microns. The lateral dimensions of the core 50 depends on the number of C4 pads on the semiconductor chip that is attached to the die foot print area 12, and may be from about 3 cm to about 7.5 cm. The front metal interconnect layers 20′ and the back metal interconnect layers 80′ are progressively built layer by layer on the top and the bottom of the core 50, respectively, by a series of processing steps. Each of the front metal interconnect layers 20′ and the back metal interconnect layers 80′ may be employed for circuit interconnection of input/output nodes, distribution of a power supply network, or distribution of a ground network. The processing steps typically involve electroless-plating, electroplating, etching, polishing, placement of dielectric resin, high temperature pressing of resin, etc. Typical temperature of the high temperature pressing of resin is about 200° C. Each of the front metal interconnect layers 20′ and the back metal interconnect layers 80′ is separated by a sheet of photosensitive resin. Laser drilling of the resin and electroplating process are used to fabricate vias that provide electrical connection between neighboring pairs of various metal interconnect layers (20′, 80′). Multi-stack vias are used to link the various metal interconnect layers (20′, 80′) that are further apart.
The front metal interconnect layers 20′ and the top insulator layers 30 are collectively called front circuit build-up layers. The back metal interconnect layers 80′ and the bottom insulator layers 70 are collectively called bottom circuit build-up layers. Since each of the various metal interconnect layers (20′, 80′) is designed to optimize electrical performance, the mechanical characteristics of each of the various metal interconnect layers (20′, 80′) are not precisely controlled.
FIGS. 2A and 2B show exemplary patterns of a pair of a top metal interconnect layer 20′ and a bottom metal interconnect layer 80′. Specifically, FIG. 2A shows an exemplary pattern of a top metal interconnect layer 20′ in which areas of the metal are represented by black areas and areas of a dielectric material, which is an organic or resin material, are represented by white areas. FIG. 2B shows an exemplary pattern of a bottom metal interconnect layer 80′ in which areas of the metal are represented by black areas and areas of the dielectric material are represented by white areas. On one hand, the top metal interconnect layers 20′ generally include dense interconnect structures made of metal lines, typically etched from a layer of metal deposited by means of a plating process. The metal may comprise Cu, Ag, Au, or Ni, and typically comprises Cu. The dense interconnect structures require a relatively high percentage of area used for electrical insulation between adjacent metal lines. Thus, the percentage of areas of the metal is relatively low, and may typically be from about 10% to about 60%. On the other hand, the bottom metal interconnect layers 80′ tend to have a continuous sheet of metal with distributed holes for vias to pass through so that the vias may be connected to BGA pads on the bottom surface of the packaging substrate. The continuous sheet of metal may comprise Cu, Ag, Au, or Ni, and typically comprises Cu. The continuous sheet of the metal is realtively high percentage of area for metal areas. Thus, percentage of areas of the metal is relatively high, and may typically be from about 40% to about 99%. Such a configuration inevitably leads to a substrate with asymmetric thermomechanical properties when viewed with respect to the plane of symmetry at the center of the core 50.
In general, a packaging substrate design with asymmetric thermomechanical parameters produces a warp when it is constructed at a high temperature and cooled down to the room temperature. Electronic manufacturing and assembly operations incorporating a packaging substrate require a warp less than a maximum acceptable level. For example, for a packaging substrate having a 55 mm×55 mm square cross-sectional area, a warp up less than 100 μm is considered acceptable. While the maximum acceptable level for the warp of a packaging substrate may vary depending on the number of front circuit build-up layers and back circuit build-up layers as well as the lateral dimensions of the packaging substrate, size of the semiconductor chip, and the thickness of the core 50, less warp is preferred since a high level of warp makes alignment and reflow of BGA solder balls difficult as well as applying a mechanical stress to C4 solder balls and compromise integrity of C4 bonding. Thus, the yield of packaging substrates may be reduced if excessive warp is introduced into the packaging substrate.
FIG. 3 shows the measured warp (corrected for initial warp at high temperature) of 12 samples of an organic packaging substrate having a 55 mm×55 mm size. A \ warp curve 150 shows the mean of the warp as a function of distance from a corner of each sample toward a diagonal corner of the sample. The direction of the measurement of the warp is shown in FIG. 1 by an arrow labeled “d.” An average warp range of about 50 μm is observed in the data from the samples. In addition, the range of the warp is not constant throughout the samples. There is a statistical distribution in the warp as a function of the distance along the diagonal of the packaging substrate. A +3 sigma warp curve 153, which is obtained by adding three times the standard variation of the 12 measured values for each distance along the diameter to the mean warp curve 150, and a −3 sigma warp curve 147, which is obtained by subtracting three times the standard variation of the 12 measured values for each distance along the diameter to the mean warp curve 150, are also shown. Statistically, 99.73% of the organic packaging substrates manufactured with the same method are expected to have less warp than the +3 sigma warp curve 153 assuming the warp is distributed according to a Gaussian probability function. In other words, 0.27% of the organic packaging substrates manufactured with the same method are expected to have more warp than the +3 sigma warp curve 153. In reality the warp distribution is more skewed towards higher warp, and the 3-sigma factor may need to be modified accordingly to cover 99.73% target. Clearly, organic packaging substrates that have unacceptable level of warp are expected to be produced in a mass production environment. The range of warp within the die foot print area 12 is marked with a dashed rectangle 112, which shows that a warp range exceeding 20 μm may be expected within the die foot print area 12.
FIG. 4 shows the result of a simulation for warp of the packaging substrate using a systematic modeling method in which thermomechanical parameters were computed from the variable metal loading, i.e., the percentage of area occupied by metal, in each of the various metal interconnect layers (20′, 80′) of the packaging substrate.
The warp may be attributed to thermomechanical parameters are asymmetric about the plane of symmetry 51 at the center of the core 50. FIG. 5 demonstrates the warp generating mechanism in which front circuit build-up layers 40′, which comprise front metal interconnect layers 20′ (See FIG. 1) and front insulator layers 30 (See FIG. 1), has a larger coefficient of thermal expansion (CTE) than back circuit build-up layers 60′, which comprise back metal interconnect layers 80′ (See FIG. 1) and back insulator layers 70 (See FIG. 1). The front circuit build-up layers 40′ contracts more relative to the back circuit build-up layers 60′ when the temperature is reduced from the processing temperature for the formation of the various circuit build-up layers (40′, 60′) to the room temperature.
In view of the above, there exists a need for a packaging substrate having reduced warp than the packaging substrates known in the art.
Particularly, there exists a need for a packaging substrate of which the warp is more immune to temperature changes than the packaging substrates known in the art.
Further, there exists a need for a systematic method for manufacturing a packaging substrate having reduced warp than the packaging substrates known in the art.